The present invention generally relates to multicore processor systems, and, more particularly, to a system and method for dynamically migrating stash transactions in multicore processor systems used in a computer network.
Multicore processor systems include one or more central processing units (CPUs) that may have a plurality of processor cores. The multiple cores of the CPUs use shared memory and input/output resources for processing data. Multicore processor systems are known for high processing speeds that render them useful for data intensive applications. By virtue of their multicore architecture, the CPUs can execute several instructions simultaneously, thus increasing processing speed considerably. This processing speed can be further increased by stashing, which entails usage of a cache memory. The cache memory is an expensive memory chip having limited storage capacity. Since cache access times are less than those of main memories, frequently accessed data is stored in the cache memory, which reduces processing time and latency associated with instruction steps that require loading/storing of data.
The multicore processor systems by virtue of their processing prowess are used as servers in computer networks such as Ethernet local area networks (LANs). The CPUs of these multicore processor systems used as servers process packets received from input/output (I/O) devices. The packets are stored in a buffer. An input output memory management unit (IOMMU) assigns a stash transaction destination identification (ID) to each packet based on the packet originating I/O device. The stash transaction destination ID includes a cache register ID of a processor core associated with the packet originating I/O device. Stash transactions are then initiated and the packets are broadcast to the various processor cores for processing. Stashing the packets in the respective cache memories of the processor cores ensures faster accesses times and thus reduced latency.
The multiple processor cores simultaneously execute different packets as threads. To efficiently manage power in the above setting, an operating system (OS) scheduler is used. The OS scheduler migrates, i.e., schedules-in and schedules-out, the threads from one core to another. The thread migration is performed in a manner that prevents any of the cores from being overloaded. Each core is provided a count of threads for processing that is in line with its capacity, thereby ensuring load balancing.
Thread migration is also essential for ensuring power efficiency in a multicore processor system. If the multicore processor system is under-utilized, the OS scheduler may choose to migrate threads to a single core and power-down the other cores. This will reduce power consumption of the multicore processing system. However, thread migration is challenging in systems that intend to benefit from stashing. Since the core to which a stash transaction will be directed is fixed at I/O device initialization, thread migration at a later stage of processing becomes cumbersome. This inflexibility may prevent the OS scheduler from effectively managing power and balancing load across the cores.
Therefore, it would be advantageous to have a system and method that enables dynamic migration of stash transactions, thereby enabling thread migration and effective power and load management and that overcomes the above-mentioned limitations of the conventional multicore systems.